This invention relates to a method and system for generating multiple system drive strengths in a memory controller.
A conventional computer system includes various types of memory components including main memory, video memory, cache memory, and buffers. Synchronous dynamic random access memories (SDRAMs) or double data rate (DDR) memories are popular memory component choices due to their relatively high access speeds and low cost.
Various techniques are used to mount these memory components, or chips, to a printed circuit board. One technique is to directly mount the memory chips to the board. To increase memory chip density, multiple memory chips may be mounted onto memory modules having interconnecting pins for connection or coupling to sockets on the board. The memory modules can be double in-line memory modules (DIMMs), or other type modules (e.g., multichip modules (MCMs)). Multiple sockets may be provided on each board to receive multiple memory modules, increasing memory capacity. Similarly, differing numbers of memory chips may be employed on any given board.
Often computers will contain a memory subsystem consisting of a number of memory chips controlled by a memory controller. The memory subsystem may comprise one or more DIMMS connected to one or more SDRAMs or DDRs. The memory controller may interface with the memory subsystem through a number of control, address, and data signals. As the number of memory chips within the memory subsystem increases, the loading placed on the control, address, and data signals also increases. The ideal output load impedance (i.e., the impedance seen on the pins caused by the load) may change from 60 ohms for a lightly loaded data signal to 15-20 ohms for a heavily loaded address signal. The system load per pin may change from 1 device load on a data line to 48 or more loads on an address line. A large change in the output impedance may cause a corresponding change in the switching characteristics of an output signal driven by the memory controller. Matching output drive strengths with output impedances will avoid these problems.
Referring to FIG. 1, one known method for matching memory controller drive strengths with output load impedance includes using an output driver 100 with resistive compensation (RCOMP) to generate predefined drive strengths of 1× (i.e., the drive strength generated by 1× driver 101 and equal to 1 times the drive strength required to drive a 60 ohm impedance) and 1.7× (i.e., the drive strength generated by 1.7× driver 102 and equal to 1.7 times the drive strength required to drive a 60 ohm impedance). The 1× driver 101 used to create the 1× drive strength includes 6 p-MOS transistors 103-108 used for pull-up compensation and 6 n-MOS transistors 109-114 used for pull-down compensation. The 1.7× driver 102 used to create the 1.7× drive strength includes 6 p-MOS transistors 115-120 used for pull-up compensation and 6 n-MOS transistors 121-126 used for pull-down compensation. The available driver drive strength options of output driver 100 are primary drive strengths 1× and 1.7×, and a combination of the two, 2.7×. The number of control signals required to generate these three drive strengths are 24, each control signal corresponding to a transistor 103-126.
By generating only three drive strengths, output driver 100 cannot ideally match a wide range of load impedances. For example, the minimum drive strength required to function in a heavily loaded system (a system with low impedance) produces significant overshoot and noise when used with a lightly loaded system (a system with high impedance).
One known method of expanding output driver 100 to produce greater granularity in drive strengths, and hence to provide better matching of impedances, is to increase the number of MOS transistors 103-126 and provide additional drivers in parallel. For example, an increase of the number of MOS transistors from 24 to 36 would provide an additional primary drive strength, resulting in seven total drive strengths.
As the number of drivers and corresponding MOS transistors increases, however, implementation of the wiring of the control signals to the output driver required for independent pull-up and pull-down compensation becomes increasingly complicated and difficult. Furthermore, the increase in the number of MOS transistor results in larger device costs and lower reliability rates.
Like reference symbols in the various drawings indicate like elements.